1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
Currently, a one-transistor/one-capacitor structure is adopted as a structure of basic cells included in a DRAM (Dynamic Random Access Memory). Along with the progress of miniaturization in semiconductor devices, a cell area per bit has been reduced from 8F2 to 6F2 and further to 4F2 in terms of an F value representing the minimum feature size. Accordingly, a vertical transistor in which channels are formed in the vertical direction of a substrate rather than in the horizontal direction thereof has been employed as a cell transistor. A three-dimensional transistor, among others, which uses a silicon pillar extending perpendicularly to the principal surface of a semiconductor substrate as a channel, has advantages of being small in occupied area and able to obtain a large drain current due to the complete depletion of carriers. Thus, even the densest layout of 4F2 is feasible using such a transistor.
Generally, one of impurity-diffusion layers to serve as a source and a drain is connected to a bit line and the other impurity-diffusion layer is connected to a capacitor of a DRAM when a vertical transistor using a silicon pillar is employed as a cell transistor of the DRAM. Under normal conditions, the capacitor is located above the cell transistor. Accordingly, the capacitor is connected to an upper impurity-diffusion layer of the silicon pillar, and a bit line is connected to a lower impurity-diffusion layer of the silicon pillar.
On the other hand, the stable operation and reliability of the DRAM are secured at above a specific level of capacitance. To that end, a method is available in which the structure of a capacitor is made three-dimensional to secure a surface area. An example in which a three-dimensionally structured capacitor is connected to a vertical transistor is proposed in, for example, JP2011-77185A.
Currently, a contact pad is used in a DRAM of a 60 nm node or later to secure a contact area between the lower electrode (storage node electrode of a capacitor, which is hereinafter referred to as “SN electrode”) and a contact plug, thereby preventing a contact resistance from increasing.
As described above, three-dimensional pillar-type transistors are adopted as cell transistors to form arrays as fine as 4F2 or the like. Consequently, allowable margins of lithography and dry etching processes for the purpose of forming contact pads have become even smaller. Thus, it has become increasingly difficult to secure a desired contact area.